The Adelsbach/VSIPL is a commercial off-the-shelf (COTS) implementation of the industry-standard API for embedded and high-performance systems, known as the Vector-Signal-Image Processing Library (VSIPL). VSIPL offers a unified, cross-vendor API standard that includes functionalities such as vector processing, FFT, digital filters, and general signal processing. It is particularly useful for applications like general signal- and synthetic aperture radar (SAR) processing. Thanks to its standardized nature, switching implementations across different vendors or platforms is straightforward, ensuring excellent future-proofing capabilities.
We aim to provide a robust, fast, portable and reliable implementation of this standard to our customers. We currently have two implementations which aim to be compliant to the VSIPL standard. Please review the documentation for further details.
- Adelsbach/VSIPL Core Light Profile
- Adelsbach/VSIPL Core Light Profile (+DP)1)
- Adelsbach/VSIPL Core Profile
- Adelsbach/VSIPL Core Profile (+DP)1)
1) +DP means double precision functionality.
The different profiles are aimed for different application scenarios; the Core Light profile is aimed at basic signal and image processing, the Core profile in addition introduces more advanced linear algebra functionality. Please refer to the documentation or the VSIPL standard for further information. A basic guideline of what is included in which profile is provided in the table below.
| Vector Views | Matrix Views | Vector Ops | Matrix Ops | Signal Processing | Linear Algebra | |
|---|---|---|---|---|---|---|
| Core Light | yes | no | some | no | some | no |
| Core | yes | yes | yes | some | some | some |
| Full | yes | yes | yes | yes | yes | yes |
A implementation of the Full profile is currently work in progress.
Please contact us for further details.
Platform Availability
Fully subject in accordance to customer requirements (Operating System, Compiler, Processor Architecture).
Standard targets:
- x86_64
- RISC-V
- PowerPC
- MIPS